1. Field of the Invention
The present invention relates to a data processing system and method for regulating a voltage supply to functional circuitry of the data processing system.
2. Description of the Prior Art
Within a data processing system, for example an integrated circuit, it is known to employ adaptive power management or dynamic voltage scaling (DVS) techniques in order to reduce the power dissipation within the system. Adaptive power management is becoming ever more important as process geometries decrease. In particular, with leading edge nanometer technology, the individual components are becoming significantly smaller in size, and the decrease in size is giving rise to a significant increase in power consumption due to leakage current (referred to herein as leakage power), leakage current being the current that is drawn by a component when it is in theory turned off. Indeed, in some instances, leakage power is becoming just as high as the dynamic power consumed by the system.
When a data processing system is designed, a nominal operating voltage can be associated with the design. During post-manufacturing tuning, that operating voltage may be modified slightly having regards to variations introduced at the time of manufacture. However, such voltage levels are always by their nature set conservatively, to ensure that the circuit will operate correctly under all expected operating conditions. However, running a system at a voltage higher than necessary has a significant impact on power consumption, and indeed this is becoming more and more of an issue as process geometries decrease for the reasons discussed above.
Adaptive power management techniques aim to reduce the power consumption by allowing system clock frequency and supply voltage to be dynamically adjusted to meet the application throughput requirements. At the system level, adaptive power management requires a voltage/frequency controller that can intelligently vary the speed of operation of the system depending on the application requirements. At the hardware implementation level, a key component is a controller that can automatically generate the minimum voltage required for a desired speed of operation, and allow the voltage to be varied having regard to the operating conditions of the system.
Various types of adaptive power management techniques have been proposed in the prior art. For example, the article “A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control” by Yong-Bin Kim et al, Department of Electrical and Computer Engineering, Northeastern University, Boston, Mass., USA, describes a system that dynamically monitors circuit performance with a slack time detector (a type of canary circuit), and aims to provide a substantially constant minimum-supply voltage for digital processors to properly operate at a given frequency with regard to different process-voltage-temperature (PVT) and load conditions. In particular, the technique adjusts or modulates the duty cycle of a switching regulator using a finite state machine that is fed by a slack time detector to set up the operating point voltage. Global operating voltages are set and the finite state machine then controls the translation of the slack detector output to the duty ratio of a pulse width modulator. The technique described in the article is said to improve yield of logic circuits incorporating the technique, due to the described adaptive voltage scaling technique compensating for variations of intrinsic parameter and operating condition by dynamically adjusting the supply voltage.
The article “Closed-Loop Adaptive Voltage Scaling Controller For Standard-Cell ASICs” by Sandeep Dhar et al, ISLPED '02, Aug. 12-14, 2002, Monterey, Calif., USA, describes a closed-loop controller for adaptive voltage scaling that uses a delay line to achieve a minimum operating frequency, and requires two separate clocks for adjusting the delay line. The approach in particular requires generating a separate sampling clock frequency for the delay line, and needs a charge pump to generate a reference voltage for a voltage regulator. A significant problem with such an approach is that the delay line used in the circuit is symmetrical and does not represent a typical worst case speed path within an integrated circuit.
The article “A Dynamic Voltage Scaled Microprocessor System” by Thomas Burd et al, IEEE Journal of Solid-State Circuits, Volume 35, No. 11, November 2000, Pages 1571 to 1580, describes a microprocessor system in which the supply voltage and clock frequency can be dynamically varied so that the system can deliver high throughput when required whilst significantly extending battery life during low speed periods. The technique described uses a voltage to frequency conversion technique and a ring oscillator to compare the output frequency with a preset value set in a voltage scheduler system control register. However, typically an application program cannot set the clock frequency since it is unaware of other programs running in a multi-tasking system. Hence, the operating system needs to understand the application demands and set a digital value in a control register. The system then uses a voltage regulation loop where the output drives a ring oscillator, and the output clock frequency of the oscillator is converted to a digital value and compared to the value set by the operating system in order to generate a feedback error. This difference in the error adjusts the voltage regulator output until the two frequencies are equalised.
The article “A Low Power Switching Power Supply for Self-Clocked Systems” by Gu-Yeon Wei et al, ISLPED 1996 Monterey, Calif., USA, also describes a dynamic voltage scaling method using a ring oscillator. In particular, the described technique uses a ring oscillator, a DC-DC converter and a PID controller as a method of predicting circuit performance in order to set a minimum regulated voltage on the chip. The ring oscillator output frequency is converted to an equivalent 9-bit binary value by counting the pulses out of the oscillator using a synchronous counter. The binary equivalent of the error between the ring oscillator and a predetermined reference frequency then feeds into the PID control block which drives the DC-DC converter to make the appropriate change to the internal voltage supply.
Whilst the above described techniques all allow savings in power consumption to be achieved, they still inherently have built in safety margins factored into the determination of a minimum operating voltage due to the way in which the provided components, whether they be a slack time detector, a delay line, or ring oscillators, feed into the determination of the operating voltage.
Accordingly, it would be desirable to provide an improved technique for regulating a voltage supply within a data processing system so as to enable further savings in power consumption to be achieved.